リンクアクセスEnglish

電気通信大学 石橋研究室

教授から

　近年、センサネットワークやメディカルエレクトロニクス等の技術が急速な発展をとげ、全てのものがインターネットに繋がるIoT(Internet of Things)の時代がこようとしています。2024年には、1兆個のセンサが絶え間なくデータを取り続け、そのデータをビッグデータ情報処理技術により、さまざまな価値のある情報が得られると予測されています。
　石橋孝一郎研究室は2011年の発足以来、低電力集積エレクトロニクスを研究室のテーマとしてIoTに関連した（１）IoTの基盤となる極低電力ＬＳＩ設計技術、エネルギーハーベスティング技術、低電力センサネットワークシステム（２）電力等の小型低電力センサー、低電力医療向けセンサ（３）センサネットワークの水産業応用と省エネルギー応用等の研究開発を進めていて、IoTによる安心安全で持続可能な社会の実現を目指しています。
現在博士課程学生1名を含む大学院生6名と卒研生7名で研究を進めていて、海外での論文発表、国際インターンシップ活動、短期留学生の受け入れ等の教育研究の国際化にも力を入れています。
このような石橋孝一郎研究室の研究教育活動に興味のある方はいつでも遠慮なくアクセスしてください。お待ちしています。

石橋孝一郎　略歴

１９５８年 東京両国生まれ
１９８０年 上智大学理工学部電気電子工学科卒
１９８５年 東京工業大学　総合理工学研究科　電子システム専攻　博士後期課程　修了（工学博士）
２０１１年 電気通信大学　情報理工学研究科　先進理工学専攻　教授
１９８５－２００１年 （株）日立製作所　中央研究所　において、高集積ＳＲＡＭ，低電力マイコンの研究
２００１－２００４年 （株）半導体理工学研究センターにおいて、低電力ＳＯＣ回路技術の研究
２００４－２０１１年 （株）ルネサスエレクトロニクスにおいて、低電力ＩＰの研究開発
２０１１年－ 電気通信大学　情報理工学研究科　教授
２０１２年－ ホーチミン理科大学、ホーチミン工科大学　客員教授
学術論文発表１１０件以上、登録済み特許１５０件以上
１９９９年 Ｒ＆Ｄ　１００　Ａｗａｒｄ
２００１年 武田研究奨励賞
電子情報通信学会　正員
IEEE Fellow

Ⅰ　著　書

  1. Editor: Koichiro Ishibashi, Kenichi Osada
    Authors: Koichiro Ishibashi, Kenichi Osada, Masanao Yamaoka, Eishi Ibe, Koji Nii, Tsukamoto Yasumasa, “Low Power and Reliable SRAM Memory Cell and Cell Array Design,” (Springer Science + Business Media, To be published in 2011)
  2. 石橋孝一郎:ＳＲＡＭの低電力化技術
    (リアライズ社、１９９８　“低消費電力、高速ＬＳＩ技術,” 桜井貴康編集委員長の第２章の執筆)
  3. Koichiro Ishibashi and Seijiro Furukawa: Formation of Smooth CoSi2 films by Solid Phase Epitaxy (KTK Scientific Publishers/Tokyo, D. Reidel Publishing Company/Dordrechit, Boston, London , 1985, Title of the book ”Layered Structures and Interface Kinetics:Their Technology and Applications,” Edited by S. Furukawa)

Ⅱ　学術論文

  1. Invited paper: K. Ishibashi, T. Fujimoto, T. Yamashita, H. Okada, Y. Arima, Y. Hashimoto, K. Sakata, I. Minematsu, Y. Itoh, H. Toda, M. Ichihashi, Y. Komatsu, M. Hagiwara, and T. Tsukada, " Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond,” IEICE Transactions on Electronics 2006 Vol.E89-C(2006) No.3 pp.250-262.
  2. Invited paper: K. Ishibashi, H. Higuchi, T. Shimbo, K. Uchiyama, K. Shiozawa, N. Hashimoto, and S. Ikeda, "Analog Circuit Design Methodology in a Low Power RISC Microprocessor," IEICE Transactions on Electronics 1998 (E81-A) 210-217. 3) Invited paper: K. Ishibashi, "High-speed CMOS SRAM Technologies for Cache Applications," IEICE Transactions on Electronics 1996 (E79-C) p.p. 724-734.
  3. M. Onouchi, Y. Kanno, M. Saen, S. Komatsu, Y. Yasu, and K. Ishibashi.; ”A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control,” IEEE Journal of Solid-State Circuits, Vol. 45(2010) , p.p.2312 - 2320
  4. S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T. Yoshihara, M. Igarashi, M. Takeuchi, K. Kawashima, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, H. Shinohara, "A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits," IEEE Journal of Solid-State Circuits, Vol. 42(2007) , p.p.820 - 829
  5. Y. Komatsu, K. Ishibashi, M. Nagata , "Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias," IEICE TRANSACTIONS on Electronics Vol.E90-C(2007) No.4 p.p.692-698
  6. Y. Komatsu, Y. Arima, and K. Ishibashi, "Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond IEICE TRANSACTIONS on Electronics Vol.E89-C(2006) No.3 pp.384-391
  7. T. Tsukada, Y.Hashimoto, K.Sakata, H.Okada, K.Ishibashi; An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs, IEEE Journal of Solid-State Circuits, vol. 40, pp. 67 - 79, January 2005.
  8. 十山圭介、三坂智、相坂一夫、在塚俊之、内山邦男、石橋孝一郎、川口博、桜井貴康、”CPU消費電力削減のための周波数-電圧協調型電力制御方式の設計ルールとフィードバック予測方式による適用“、電子情報通信学会論文誌　D-I, Vol.J87-D-I, (2004) , No.4, pp.452-461.
  9. Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saito; 3-D device modeling for SRAM soft-error immunity and tolerance analysis, IEEE Trans. Electron Devices, Vol. 51, pp. 378 - 388, March 2004.
  10. Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi; 0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme, IEEE Journal of Solid-State Circuits, vol. 39, pp. 934 - 940, June 2004.
  11. Shuji Ikeda, Yasuko Yoshida, Shiro Kamohara, Koichi Imato, Koichro Ishibashi, Kazuo Takahashi; Threshold voltage-related soft error degradation in a TFT SRAM cell, IEEE Trans. Electron Devices, Vol. 50, pp. 391 - 396, February 2003.
  12. Shuji Ikeda, Yasuko Yoshida, Koichiro Ishibashi, Yasuhiro Mitsui; Failure analysis of 6T SRAM on low-voltage and high-frequency operation, IEEE Trans. Electron Devices, Vol. 50, pp. 1270 - 1276, May 2003.
  13. Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi; 16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors, IEEE Journal of Solid-State Circuits, vol. 38(2003) , pp. 1952 - 1957, November 2003.
  14. S. Shukuri, K. Ishibashi, K. Norisue, M. Yamaoka, K. Yanagisawa, "A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit", IEEE Journal of Solid-State Circuits, Volume: 37 Issue: 5 , May 2002　Page(s) : 599 -604.
  15. M. Miyazaki, G. Ono and K. Ishibashi, "A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias," IEEE Journal of Solid-State Circuits, Volume: 37 Issue: 2 , Feb 2002　Page(s) : 210 -217.
  16. K. Osada, Luke Shin Jinuk; M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda and K. Ishibashi, "Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell," IEEE Journal of Solid-State Circuits, Volume: 36 Issue: 11 , Nov 2001 Page(s) : 1738 -1744.
  17. Shoji SHUKURI Kazumasa YANAGISAWA Koichiro ISHIBASHI, "CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip," IEICE TRANSACTIONS on Electronics Vol.E84-C(2001) No.6 pp.734-739
  18. 宮崎祐行　石橋孝一郎、”低電力システムクロック発生回路向け並列位相比較型ディレーロックドループ、”　電子情報通信学会論文誌Ｃ(2000) 、Vol.J83-C No.6,　p.p. 502-508
  19. K. Osada, H. Higuchi, K. Ishibashi, N. Hashimoto, and K. Shiozawa, "A 2-ns Access, 285-MHz, Two-port Cache Macro using Double Global Bit-Line Pairs," IEICE Transactions on Electronics 2000 (E83-C) 109-114
  20. H. Mizuno and K. Ishibashi, "A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio," IEEE Transactions on Very Large Scale Integration (VLSI) Systems1999(7,1) 139-144.
  21. H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S . Ikeda and K.Uchiyama, "An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode," IEEE Journal of Solid-State Circuits 1999 (34.11) 1492-1500.
  22. M. Minami, N. OhkiH. Ishida, T. Yamanaka, A. Shimizu, K. Ishibashi, A. Satoh, T. Kure, T. Nishida, and T. Nagano, “A 6.93um2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory,” IEICE Transactions on Electronics 1997 (E80-C) 590-596.
  23. Y. Shimazaki, K. Norisue, K. Ishibashi, and H. Maejima, "An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors," IEICE Transactions on Electronics 1996 (E79-C) 1693-1698
  24. H. Mizuno, N. Matsuzaki, K. Osada, T. Shinbo, N. Ohki, H. Ishida, K . Ishibashi and T.Kure, "A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators," IEEE Journal of SOLID-STATE CIRCUITS 1996 (31.11) 1618-1624
  25. G. Ono, M. Miyazaki and K. Ishibashi, "Quantitative Study of SA-Vt CMOS Scheme Based on the Evaluation of Device Fluctuation," 2000 International Conference on Solid State Devices and Materials, E-5-2.
  26. H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S . Ikeda and K.Uchiyama, "A 18 μA-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode," 1999 IEEE International Solid-state Circuits Conference P.P. 280-281.
  27. M. Miyazaki and K. Ishibashi, "A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems," １９９９. AP-ASIC '99. The First IEEE Asia Pacific Conference P.P. 396 -399.
  28. O. Nishii, F. Arakawa, K. Ishibashi, S. Nakano, T. Shimura, K. Suzuki, M. Tachibana, . Totsuka, T. Tsunoda, K. Uchiyama, T. Yamada, T. Hattori, H. Maejima, N. Nakagawa, S. Narita, M. Seki, Y. Shimazaki, R. Satomura, T. Takasuga and A. Hasegawa, "A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit," 1998 IEEE International Solid-state Circuits Conference, SA18.1 P.P. 288-289.
  29. H. Mizuno and K. Ishibashi, "A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators," 1998 IEEE International Solid-state Circuits Conference, SP25.5 P.P. 404-405.
  30. M. Miyazaki, H. Mizuno, and K. Ishibashi, "A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls," 1998 International Symposium on Low Power Electronics and Design P.P 48-53
  31. K. Ishibashi, H. Higuchi, Y. Shimbo, F. Arakawa, O. Nishii, N. Nakagawa, H. Maejima, K. Osada, K. Norisue, R. Satomura, H. Aoki, Y. Shimazaki, K. Tanaka, T. Hattori, K. Shiozawa, K. Kudo, K. Uchiyama, S. Narita, J. Nishimoto, T. Nagano, S. Ikeda, K. Kuroda, T. Takeda, and N. Hashimoto, "The Design Of 300MIPS Microprocessor With A Full Associative TLB For Hand-held PC OS," 1997 Symposium on VLSI Circuits, 2-1 P.P. 9-10
  32. K. Osada, H. Higuchi, K. Ishibashi, N. Hashimoto, K. Shiozawa, "A Lean-power Gigascale LSI Using Hierarchical Vbb Routing Scheme With Frequency Adaptive Vt CMOS," 1997 IEEE International Solid-state Circuits Conference, SP24.4 P.P. 402-403.
  33. H. Mizuno, M. Miyazaki, K. Ishibashi, Y. Nakagome, and T. Nagano, "A Lean-power Gigascale LSI Using Hierarchical V/sub bb/ Routing Scheme With Frequency Adaptive V/sub t/ CMOS," 1997 Symposium on VLSI Circuits, P.P 95-96
  34. H. Mizuno, N. Matsuzaki, K. Osada, T. Shinbo, N. Ohki, H. Ishida, K . Ishibashi and T.Kure, "A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators," 1996 IEEE International Solid-state Circuits Conference, P.P 152-153 39) H. Mizuno and K. Ishibashi," A cost-oriented two-port unified cache for low-power RISC microprocessors," 1996 Symposium on VLSI Circuits, P.P. 72-73.
  35. K. Ishibashi, K. Komiyaji, H. Toyoshima, R. Minami, N. Ohki, H. Ishida, T. Yamanaka,T .Nagano, and T. Nishida, "A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL," 1995 IEEE International Solid-state Circuits Conference, FA18.5 P.P. 308-309.
  36. S. Narita, K. Ishibashi, S. Tachibana, K. Norisue, Y. Shimazaki, J. Nishimoto, K. Uchiyama, T. Nakazawa, K. Hirose, I. Kudoh, R. Izawa, S. Matsui, S. Yoshioka, M. Yamamoto, I. Kawasaki, "A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing," 1995 Symposium on VLSI Circuits, P.P. 59-60.
  37. Y. Shimazaki, K. Ishibashi, K. Norisue, S. Narita, K. Uchiyama, T. Nakazawa, I. Kudoh, R. Izawa, S. Yoshioka, S. Tamaki, S. Nagata, I. Kawasaki, K. Kuroda, "An automatic-power-save cache memory for low-power RISC processors," IEEE Symposium on Low Power Electronics and design 1995, P.P. 58-59.
  38. M. Minami, N. OhkiH. Ishida, T. Yamanaka, A. Shimizu, K. Ishibashi, A. Satoh, T. Kure, T. Nishida, and T. Nagano, "A 6.93-μm2 n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits," 1995 Symposium on VLSI Technology, 2-3 P.P. 13-14.
  39. K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A . Fuk ami, N.Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano and T. Nishida, A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers," 1994 Symposium on VLSI Circuits, 10.1 P.P. 107-108.
  40. K. Ishibashi, K. Takasugi, T. Hashimoto and K. Sasaki, "A 12.5ns 16Mb CMOS SRAM," 1993 Symposium on VLSI Circuits, 12-4 P.P. 103-104.
  41. Shuji Ikeda, Kyoichiro Asayama, Naotaka Hashimoto, Eri Fujita, Yasuko Yoshida, Atsuyosi Koike, Toshiaki Yamanaka, Koichiro Ishibashi, Satoshi Meguro; A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs, IEDM Tech. Dig., pp. 809 - 812, December 1993.
  42. K. Ishibashi, K. Takasugi, T. Hashimoto and K. Sasaki., "A 1 V TFT-load SRAM using a two-step word-voltage method," 1992 IEEE International Solid-state Circuits Conference, FA13.1 P.P. 206-207.
  43. K. Sasaki, K. Ishibashi, K. Ueda, K. Komiyaji, T. Yamanaka, N.Hashimoto, H.T oyos him a,F .Kojima and A. Shimizu, A 7 ns 140 mW 1 Mb CMOS SRAM with current sense amplifier," 1992 IEEE International Solid-state Circuits Conference, FA13.2 P.P. 208-209.
  44. K. Ishibashi, K. Sasaki, T. Yamanaka, H. Toyoshima, and F. Kojima, "A 1.7V Adjustable I/O Interface for Low Voltage Fast SRAMs," 1991 Symposium on VLSI Circuits, 10-4 P.P. 97-98
  45. O. Minato, K. Ishibashi, "Low power, low voltage memories for portable electronics," 1991 International Symposium on Technology, Systems, and Applications, P.P. 354-357
  46. K. Sasaki, K. Ishibashi, T. Yamanaka, K. Shimohigashi, N. Moriwaki, S. Honjo, S. Ikeda, A Koike, S, Meguro and O. Minato, "A 23 ns 4 Mb CMOS SRAM with 0.5 μA standby current," 1990 IEEE International Solid-state Circuits Conference, TPM8.3 P.P. 130-131.
  47. T. Yamanaka, N. Hasegawa, T. Tanaka, K. Ishibashi, T. Hashimoto, A. Shimizu, N. Hashimoto, K. Sasaki, T. Nishida, and E. Takeda, "A 5.9 μm2 super low power SRAM cell using a new phase-shift lithography," 1990 International Electron Devices Meeting, 18.3.1 P.P. 477-480.
  48. K. Ishibashi, T. Yamanaka and K. Shimohigashi, "An alpha-immune, 2V supply voltage SRAM using polysilicon PMOS load cell," 1989 Symposium on VLSI Circuits, 3-5 P.P. 29-30.
  49. K. Sasaki, S. Hanamura, K. Ishibashi, T. Yamanaka, N. Hashimoto, T. Nishida, K. Shimohigashi, and S. Honjo, "A 9 ns 1 Mb CMOS SRAM," 1989 IEEE International Solid-state Circuits Conference, WAM2.5 P.P. 34-35.
  50. T. Yamanaka, T. Hashimoto, N. Hashimoto, T. Nishida, A. Shimuzu, K. Ishibashi, Y. Sakai, K. Shimohigashi, E. Takeda, "A 25 μm2, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity," 1988, Electron Devices Meeting,. Technical Digest., International , 11-14 Dec 1988 P.P. 48-51.
  51. O. Minato, T. Sasaki, S. Honjo, K. Ishibashi, Y. Sasaki, N. Moriwaki, K. Nishimura, Y. Sakai, S. Meguro, M. Tsunematsu, and T. Masuhara, "A 42ns 1Mb CMOS SRAM," 1987 IEEE International Solid-state Circuits Conference, FAM19.6 P.P. 260 -261
  52. K. Ishibashi and S. Furukawa, "Formation of SPE-CoSi2 Submicron Line by Lift Off Using Selective Reaction," 1984 International Conference on Solid-State Devices and Materials, A-2-6.
  53. K. Ishibashi and S. Furukawa, "Si permeable base transistor by metal/semiconductor hetero-epitaxy," 1984 International Electron Devices Meeting.
  54. K. Ishibashi, H. Ishiwara, and S. Furukawa, "Study on Formation of Solid-Phase-Epitaxial CoSi2 Films and Patterning Effects",1983 International Conference on Solid-State Devices and Materials, A-1-2
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Ⅲ　国際会議プロシーディングス等

  1. Invited: Koichiro Ishibashi, Shigeki Ohbayashi, Katsumi Eikyu, Motoaki Tanizawa, Yasumasa Tsukamoto, Kenichi Osada, Masayuki Miyazaki, and Masanao Yamaoka, "Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models," 2006 International Electron Devices Meeting, (2006 IEDM, San Francisco) , Digest p.p.199-202.
  2. Invited: Koichiro Ishibashi, "Low Power Technology Development at STARC," The Second International Worksyop on Nanoelectronics for Terra-bit Information Processing, Jan, 2004 Hiroshima, Japan.
  3. Invited: K. Ishibashi and T. Yamashita, "Low Power SoC Project in STARC", 2003 International Symp. on VLSI technology, Systems and Applications, Oct. 2003, (2003 VLSI TSA, Shinchu, Taiwan) Proceedings pp.180-183.
  4. M. Onouchi, Y. Kanno, M. Saen, S. Komatsu, Y. Yasu, K. Ishibashi, ” A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control, ”A-SSCC 2009. Fukuoka, Japan p.p. 85 ? 88.
  5. J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, K. Asada, ” Resonant supply noise canceller utilizing parasitic capacitance of sleep blocks,” VLSI Circuits symposium 2010, Honolulu Hawaii, p.p. 119 ? 120.
  6. N. Mizuguchi, K. Takeuchi, H. Tobe, P. Lee and K. Ishibashi, “Hot-CarrierAC Lifetime Enhancement due to Wire Resistance Effect (WRE) in 45nm CMOS Circuits,” SSDM 2008 , Sep, 25th, Tsukuba Japan.
  7. Y. Kanno, K. Yoshizumi, Y. Yasu, K. Ishibashi, H. Mizuno, “Dynamic voltage boost (DVB) method for improving power integrity of low-power multi-processor SoCs,” VLSI Circuit Symposium 2008 , Digest p.p. 148-149.
  8. K. Fukuoka, O. Ozawa, R. Mori, Y. Igarashi, T. Sasaki, T. Kuraishi, Y. Yasu and K. Ishibashi, "A 1.92μs-Wake-Up Time Thick-Gate-Oxide Power Switch Technique for Ultra Low-Power Single- Chip Mobile Processors," VLSI Circuit Symposium 2007 , Digest p.p. 128-129.
  9. S. Ohbayashi, M. Yabuuchi, Y. Oda, S. Imaoka, K. Usui, T. Yonezu, T. Iwamoto, K. Nii, Y. Tsukamoto, M. Arakawa, T. Uchida, M. Okada, A. Ishii, H. Makino, K. Ishibashi, and H. Shinohara, "A 65-nm embedded SRAM with Wafer Level Burn-in Mode, Leak-bit Redundancy and E-trim Fuse for Known Good Die," ISSCC 2007, 27.2
  10. Osamu Ozawa, Kazuki Fukuoka, Yasuto Igarashi, Takashi Kuraishi, Yosihiko Yasu, Yukio Maki, Takashi Ipposhi, Toshihiko Ochiai, Masayoshi Shirahata, Koichiro Ishibashi; Low power SOC design using partial-trench-isolation ABC SOI (PTI-ABC SOI) for sub-100-nm LSTP technology, Symp. VLSI Circuits 2006, Dig. , pp. 186 - 187.
  11. S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M.Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto,M. Inuishi, H. Makino, K. Ishibashi and H. Shinohara, "A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits," VLSI Circuit Symposium 2006, Digest p.p. 20-21.
  12. K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi and H. Shinohara, "A 65nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC," VLSI Circuit Symposium 2006, Digest p.p. 162-163.
  13. Motoi Ichihashi, Haruki Toda, Yasuo Itoh, Koichiro Ishibashi; 0.5V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process, Symp. VLSI Circuits 2005, Dig. , pp. 366 - 369.
  14. Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara: Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD 2005: 398-405
  15. Yukio Arima, Takahiro Yamashita, Yoshihide Komatsu, Tetsuya Fujimoto, Koichiro Ishibashi; Cosmic-ray immune latch circuit for 90nm technology and beyond, IEEE International Solid-State Circuits Conference, vol. XVII, pp. 492 - 493, February 2004.
  16. Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi; An on-chip active decoupling circuit to suppress crosstalk in deep sub-micron CMOS mixed-signal SoCs, IEEE International Solid-State Circuits Conference, vol. XVII, pp. 160 - 161, February 2004.
  17. Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi; A soft-error hardened latch scheme for SoC in a 90nm technology and beyond, 2004 IEEE Custom Integrated Circuits Conference, May 2004.
  18. Koichiro Ishibashi, Takahiro Yamashita, Yukio Arima, Isao Minematsu, Tetsuya Fujimoto; A 9μW 50MHz 32b adder using a self-adjusted forward body bias in SoCs, IEEE International Solid-State Circuits Conference, vol. XLVI, pp. 116 - 117, February 2003.
  19. Hiroyuki Okada, Yasuyuki Hashimoto, Kohji Sakata, Toshiro Tsukada, Koichiro Ishibashi; Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash ADCs using 0.13-um generic CMOS technology, Proceedings of the 29th European Solid-State Circuits Conference, pp. 711 - 714, September 2003.
  20. Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi; 16.7fA/Cell tunnel-leakage-suppressed 16Mb SRAM for handling cosmic-ray-induced multi-errors, IEEE International Solid-State Circuits Conference, vol. XLVI, pp. 302 - 303, February 2003.
  21. K. Aisaka, T. Aritsuka, K. Ishibashi, H. Kawaguchi, S. Misaka, T. Sakurai, K. Toyama, K. Uchiyama, "Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder," 2002 Symposium on VLSI Circuits P.P .216-217.
  22. M. Yamaoka, K. Osada, and K. Ishibashi, “0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme”, 2002 Symposium on VLSI Circuits P.P. 170-173.
  23. Y. Arima, K. Ishibashi, T. Yamashita, "A V-driver circuit for lowering power of sub-0.1/spl mu/m bus," 2002 Aia-Pacific ASIC, P.P. 267-270.
  24. Shoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi; CMOS process compatible ie-flash(inverse gate electrode flash) technology for system-on-a chip, 2001 IEEE Custom Integrated Circuits Conference, May 2001.
  25. K. Osada, J. Shin, M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda and K. Ishibashi," Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell," 2001 IEEE International Solid-state Circuits Conference, 11.1 p.p. 168-169.
  26. K. Ishibashi, S. Shukuri, K. Tanagisawa, "CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip," 2001 CICC P.P. 179-182.)
  27. M. Yamaoka, K. Yanagiwawa, S. Shukuri, K. Norisue, and K. Ishibashi, "A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit" 2001 Symposium on VLSI Circuits P.P. 71-72
  28. M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, and K. Ishibashi, "A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias," 2000 IEEE International Solid-State Circuits Conference, 25.6 P.P. 420 -421.
  29. G. Ono, M. Miyazaki and K. Ishibashi, "Quantitative Study of SA-Vt CMOS Scheme Based on the Evaluation of Device Fluctuation," 2000 International Conference on Solid State Devices and Materials, E-5-2.
  30. H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S . Ikeda and K.Uchiyama, "A 18 μA-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode," 1999 IEEE International Solid-state Circuits Conference P.P. 280-281.
  31. M. Miyazaki and K. Ishibashi, "A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems," １９９９. AP-ASIC '99. The First IEEE Asia Pacific Conference P.P. 396 -399.
  32. O. Nishii, F. Arakawa, K. Ishibashi, S. Nakano, T. Shimura, K. Suzuki, M. Tachibana, . Totsuka, T. Tsunoda, K. Uchiyama, T. Yamada, T. Hattori, H. Maejima, N. Nakagawa, S. Narita, M. Seki, Y. Shimazaki, R. Satomura, T. Takasuga and A. Hasegawa, "A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit," 1998 IEEE International Solid-state Circuits Conference, SA18.1 P.P. 288-289.
  33. H. Mizuno and K. Ishibashi, "A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators," 1998 IEEE International Solid-state Circuits Conference, SP25.5 P.P. 404-405.
  34. M. Miyazaki, H. Mizuno, and K. Ishibashi, "A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls," 1998 International Symposium on Low Power Electronics and Design P.P 48-53
  35. K. Ishibashi, H. Higuchi, Y. Shimbo, F. Arakawa, O. Nishii, N. Nakagawa, H. Maejima, K. Osada, K. Norisue, R. Satomura, H. Aoki, Y. Shimazaki, K. Tanaka, T. Hattori, K. Shiozawa, K. Kudo, K. Uchiyama, S. Narita, J. Nishimoto, T. Nagano, S. Ikeda, K. Kuroda, T. Takeda, and N. Hashimoto, "The Design Of 300MIPS Microprocessor With A Full Associative TLB For Hand-held PC OS," 1997 Symposium on VLSI Circuits, 2-1 P.P. 9-10
  36. K. Osada, H. Higuchi, K. Ishibashi, N. Hashimoto, K. Shiozawa, "A Lean-power Gigascale LSI Using Hierarchical Vbb Routing Scheme With Frequency Adaptive Vt CMOS," 1997 IEEE International Solid-state Circuits Conference, SP24.4 P.P. 402-403.
  37. H. Mizuno, M. Miyazaki, K. Ishibashi, Y. Nakagome, and T. Nagano, "A Lean-power Gigascale LSI Using Hierarchical V/sub bb/ Routing Scheme With Frequency Adaptive V/sub t/ CMOS," 1997 Symposium on VLSI Circuits, P.P 95-96
  38. H. Mizuno, N. Matsuzaki, K. Osada, T. Shinbo, N. Ohki, H. Ishida, K . Ishibashi and T.Kure, "A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators," 1996 IEEE International Solid-state Circuits Conference, P.P 152-153
  39. H. Mizuno and K. Ishibashi," A cost-oriented two-port unified cache for low-power RISC microprocessors," 1996 Symposium on VLSI Circuits, P.P. 72-73.
  40. K. Ishibashi, K. Komiyaji, H. Toyoshima, R. Minami, N. Ohki, H. Ishida, T. Yamanaka,T .Nagano, and T. Nishida, "A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL," 1995 IEEE International Solid-state Circuits Conference, FA18.5 P.P. 308-309.
  41. S. Narita, K. Ishibashi, S. Tachibana, K. Norisue, Y. Shimazaki, J. Nishimoto, K. Uchiyama, T. Nakazawa, K. Hirose, I. Kudoh, R. Izawa, S. Matsui, S. Yoshioka, M. Yamamoto, I. Kawasaki, "A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing," 1995 Symposium on VLSI Circuits, P.P. 59-60.
  42. Y. Shimazaki, K. Ishibashi, K. Norisue, S. Narita, K. Uchiyama, T. Nakazawa, I. Kudoh, R. Izawa, S. Yoshioka, S. Tamaki, S. Nagata, I. Kawasaki, K. Kuroda, "An automatic-power-save cache memory for low-power RISC processors," IEEE Symposium on Low Power Electronics and design 1995, P.P. 58-59.
  43. M. Minami, N. OhkiH. Ishida, T. Yamanaka, A. Shimizu, K. Ishibashi, A. Satoh, T. Kure, T. Nishida, and T. Nagano, "A 6.93-μm2 n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits," 1995 Symposium on VLSI Technology, 2-3 P.P. 13-14.
  44. K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A . Fuk ami, N.Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano and T. Nishida, A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers," 1994 Symposium on VLSI Circuits, 10.1 P.P. 107-108.
  45. K. Ishibashi, K. Takasugi, T. Hashimoto and K. Sasaki, "A 12.5ns 16Mb CMOS SRAM," 1993 Symposium on VLSI Circuits, 12-4 P.P. 103-104.
  46. Shuji Ikeda, Kyoichiro Asayama, Naotaka Hashimoto, Eri Fujita, Yasuko Yoshida, Atsuyosi Koike, Toshiaki Yamanaka, Koichiro Ishibashi, Satoshi Meguro; A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs, IEDM Tech. Dig., pp. 809 - 812, December 1993.
  47. K. Ishibashi, K. Takasugi, T. Hashimoto and K. Sasaki., "A 1 V TFT-load SRAM using a two-step word-voltage method," 1992 IEEE International Solid-state Circuits Conference, FA13.1 P.P. 206-207.
  48. K. Sasaki, K. Ishibashi, K. Ueda, K. Komiyaji, T. Yamanaka, N.Hashimoto, H.T oyos him a,F .Kojima and A. Shimizu, A 7 ns 140 mW 1 Mb CMOS SRAM with current sense amplifier," 1992 IEEE International Solid-state Circuits Conference, FA13.2 P.P. 208-209.
  49. K. Ishibashi, K. Sasaki, T. Yamanaka, H. Toyoshima, and F. Kojima, "A 1.7V Adjustable I/O Interface for Low Voltage Fast SRAMs," 1991 Symposium on VLSI Circuits, 10-4 P.P. 97-98
  50. O. Minato, K. Ishibashi, "Low power, low voltage memories for portable electronics," 1991 International Symposium on Technology, Systems, and Applications, P.P. 354-357
  51. K. Sasaki, K. Ishibashi, T. Yamanaka, K. Shimohigashi, N. Moriwaki, S. Honjo, S. Ikeda, A Koike, S, Meguro and O. Minato, "A 23 ns 4 Mb CMOS SRAM with 0.5 μA standby current," 1990 IEEE International Solid-state Circuits Conference, TPM8.3 P.P. 130-131.
  52. T. Yamanaka, N. Hasegawa, T. Tanaka, K. Ishibashi, T. Hashimoto, A. Shimizu, N. Hashimoto, K. Sasaki, T. Nishida, and E. Takeda, "A 5.9 μm2 super low power SRAM cell using a new phase-shift lithography," 1990 International Electron Devices Meeting, 18.3.1 P.P. 477-480.
  53. K. Ishibashi, T. Yamanaka and K. Shimohigashi, "An alpha-immune, 2V supply voltage SRAM using polysilicon PMOS load cell," 1989 Symposium on VLSI Circuits, 3-5 P.P. 29-30.
  54. K. Sasaki, S. Hanamura, K. Ishibashi, T. Yamanaka, N. Hashimoto, T. Nishida, K. Shimohigashi, and S. Honjo, "A 9 ns 1 Mb CMOS SRAM," 1989 IEEE International Solid-state Circuits Conference, WAM2.5 P.P. 34-35.
  55. T. Yamanaka, T. Hashimoto, N. Hashimoto, T. Nishida, A. Shimuzu, K. Ishibashi, Y. Sakai, K. Shimohigashi, E. Takeda, "A 25 μm2, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity," 1988, Electron Devices Meeting,. Technical Digest., International , 11-14 Dec 1988 P.P. 48-51.
  56. O. Minato, T. Sasaki, S. Honjo, K. Ishibashi, Y. Sasaki, N. Moriwaki, K. Nishimura, Y. Sakai, S. Meguro, M. Tsunematsu, and T. Masuhara, "A 42ns 1Mb CMOS SRAM," 1987 IEEE International Solid-state Circuits Conference, FAM19.6 P.P. 260 -261
  57. K. Ishibashi and S. Furukawa, "Formation of SPE-CoSi2 Submicron Line by Lift Off Using Selective Reaction," 1984 International Conference on Solid-State Devices and Materials, A-2-6.
  58. K. Ishibashi and S. Furukawa, "Si permeable base transistor by metal/semiconductor hetero-epitaxy," 1984 International Electron Devices Meeting.
  59. K. Ishibashi, H. Ishiwara, and S. Furukawa, "Study on Formation of Solid-Phase-Epitaxial CoSi2 Films and Patterning Effects",1983 International Conference on Solid-State Devices and Materials, A-1-2
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Ⅳ　解説論文，レビュー論文

  1. Web 雑誌 マイコミジャーナル, 【レポート】増大するプロセッサの消費電力(1) - 省電力化のセオリーとは　2003/04/04
    http://journal.mycom.co.jp/news/2003/04/04/21.html
  2. Web 雑誌 マイコミジャーナル, 【レポート】増大するプロセッサの消費電力(2) - 基板バイアス技術を採用　2003/04/04
    http://journal.mycom.co.jp/news/2003/04/04/22.html
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Ⅴ　学会口頭発表

  1. K. Ishibashi, "LSI industry requirement to SOI for mobile applications" in the 3rd FDSOI Workshop;”, 2010 Tokyo.
  2. K. Ishibashi, "Adaptive Design of SRAM Memory Cells" in the special evening session” Chip Breakthroughs and Address Circuit/Device Interactions;”, 2007 IEDM, Washington D.C.
  3. K. Ishibashi, "Adaptive body bias techniques for low power SOC," in the Microprocessor Forum, 2007 ISSCC, San Francisco.
  4. 石橋孝一郎「オンチップメモリの低電力化と微細化への挑戦」、第９回システムＬＳＩワークショップ（2005, 小倉) 、Digest p.p. 111-122 4) 　K. Ishibashi, “低消費電力プロセッサ　回路技術とその動向”, in the Tutorial, 2005 SACSIS (the Annual Symposium on Advanced Computing Systems and Infrastructures) , (2005, つくば) 5)　石橋孝一郎「論理回路の低電力技術とボディーゲーティング法の提案」SEMI FORUM JAPAN 2004, プロセスデバイス技術セミナー P.P. 47-66.　（2004 大阪) 6) K. Ishibashi, “Low power SoC project at STARC: low voltage and high speed digital and analog circuits,” Seminar @IMEC (Nov. 7th, 2003, Leuven, Belgium). 7) 石橋孝一郎（特別公演) 「論理回路のソフトエラー：低電力ＬＳＩの新しい課題」、ＳＴＲＪ２００３年度ワークショップ
  5. 石橋孝一郎「ＳＴＡＲＣにおける低電力技術開発」、第６回システムＬＳＩワークショップ（200２)
  6. K. Ishibashi, “Low Power Memory”, in the short course, 2001 SSDM(International Symposium on Solid-State Devices and Materials) , Tokyo.
  7. K. Ishibashi, "Substrate-Bias Techniques for SH4", in the short course, 2001 VLSI Circuit Symposium, Kyoto.Ⅴ　学会口頭発表，未刊行論文
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Ⅵ　表彰等

  1. 2010 平成２２年度　関東地方発明表彰　発明奨励賞
    　　表彰内容　“半導体集積回路装置, 特許第4106033号”
  2. 2005 IEEE Fellow Award
    　　表彰内容　“For technical contributions to developments of low-power SRAMs and MCUs.”
  3. 2003 Technical-Paper Presentations at ISSCC 1964-2003 on the occasion of the ISSCC 50th anniversary
  4. 2001 2001年度武田研究奨励賞
    　　題名「マイコンの超低電力化回路技術」
  5. 1999 R&D 100 1999 (selected by R & D 100 magazine) Title “Development of SH4(SH-7750 series) microprocessors”
  6. 1988 手島記念財団　手島賞　論文賞 "Formation of Uniform Solid-Phase Epitaxial CoSi2 Films by Patterning Method"
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Ⅶ　半導体業界委員等

  1. 2011～ 独立行政法人 新エネルギー・産業技術総合開発機構（NEDO） 技術委員
  2. 2005～ 独立行政法人　科学技術振興機構　（JST) 戦略的創造研究事業（CREST) 研究領域：情報システ2010～ ムの超低消費電力化を目指した技術革新と統合化技術 領域アドバイザー
  3. 2002～2008 International Technology Roadmap for Semiconductor (ITRS) 　Design TWG member
  4. 2002～2008 (社) 電子情報技術産業協会（JEITA) 半導体ロードマップ専門委員会（STRJ) 設計タスクフォース 委員
    　（同2006-2007年度　設計 TF 主査)
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Ⅷ　学会活動等

  1. 2011 Rump session panelist, ISSCC 2011
  2. 2010 Rump session panelist, VLSI Symposia 2010
  3. 2008 Panelist WRTLT’08
    (IEEE Workshop on RTL and High Level Testing) 2007 Special Evening Session Speaker, IEDM 2008
  4. 2007 Microprocessor Forum lecturer, ISSCC 2007
  5. 2006 Invited Paper Presentation, IEDM 2006
  6. 2004 Rump session organizer, VLSI Circuit symposium 2004
  7. 2002 Short course organizer, VLSI Circuit symposium 2002 2001 Short course lecturer, SSDM
  8. 2001 (International Conference on Solid-State Devices and Materials)
  9. 2001 Short course lecturer, VLSI Circuit symposium 2001
  10. 2000 Session associate chairman, ISSCC 2000
  11. 1999 Session associate chairman, ISSCC 1999
  12. 1998 Session chairman, ISSCC 1998
  13. 1997 Session chairman, ISSCC 1997
  14. 1997-2000 Program committee member, ISSCC
  15. 1995 Rump session panelist, VLSI Circuit symposium 1995 Materials
  16. 2005 Guest editor IEICE trans. Electron, Vol.E88-C(2005) No.4
  17. “Special Section on Low-Power LSI and Low-Power IP”
  18. 2004 Associate guest editor, IEICE trans. Electron, vol. E87-C
  19. 2002～2006 IEICE Transactions-A 和文誌編集委員 1995～1998 IEICE Transactions-C和文誌編集委員
  20. 1996 Associate guest editor, IEICE trans. Electron, vol. E79-C
  21. 1996 Secretary of the guest editor, IEICE tran.
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